The present invention relates to the control and monitoring of power switches. It more particularly relates to the control of power switches, one terminal of which is at a floating reference voltage, and level translating circuits designed to transmit, from a control circuit at a fixed reference voltage, orders to a power switch control circuit, or conversely, to receive monitoring information.
FIG. 1 very schematically shows the control of a power switch 1 arranged in series with another power switch 2 connected to the ground, these two switches being part, for example, of a bridge circuit. The junction of these two switches is at a floating voltage V.sub.F liable, on the one hand, to reach high voltages and, on the other hand, to be submitted to very abrupt voltage variations, for example several tens of thousands volts per microsecond. The control unit comprises, on the one hand, a control circuit 10 receiving external orders on a terminal 11 and connected to the ground and, on the other hand, a gate control circuit corresponding to each switch, and especially a gate control circuit 20 for switch 1. Between circuits 10 and 20 is inserted a level translating circuit 30 connected to the ground, as well as to a floating voltage V'.sub.F varying with the floating voltage V.sub.F.
The gate control circuit 20 is necessarily connected to the floating voltage V.sub.F. Therefore, problems are encountered as regards the level translation between the control and monitoring circuits and there generally are two drawbacks, on the one hand, energy consumption when switch 1 is conductive, due to current then flowing in translator 30 submitted to voltage V'.sub.F and, on the other hand, sensitivity to parasitic pulses resulting from fluctuations of the floating voltage V.sub.F and therefore of V'.sub.F.
In order to solve consumption problems, pulse control circuits, such as the one illustrated in FIG. 2, have been provided. In this circuit, the portion of the gate control 20 comprises a RS flip-flop 21, the output of which is applied through an amplifier 22 to the gate of the power transistor 1. Each input R and S of the flip flop receives one of the outputs of the level translating circuit, 31 and 32, respectively. The whole set of circuits 21, 22, 31 and 32 is connected to the floating voltage V'.sub.F. The level translating circuits 31 and 32 receive control pulses from the control circuit 10 through circuit 33 and 34.
The advantage of this type of circuit is to avoid a significant dissipation of energy in the translating circuit 30 but the circuit is sensitive to parasitic pulses on source V.sub.L or to abrupt variations in voltage V.sub.F. In fact, there unavoidably are stray capacitances, for example MOS transistors capacitances 35 and 36, liable to get charged due to abrupt voltage variations and, on account of abrupt variations in the floating voltage value, to let appear parasitic pulses across the terminals or inside circuits 31 and 32, which may cause spurious triggering of the RS flip-flop 21.